Low power has emerged as a principal theme in today’s electronics industry. To achieve an optimized design, Flip-flops (FF) plays a vital role in low-power digital systems. In the existing method, clock gating with different voltage level signals were implemented such as ,low swing (LS) clock signal and conventional clock, throughout the entire clock network. Thus, power savings was maximized. But, the existing method had a drawback, such as area overhead, had not been quantified. In the proposed method, a restructured DFF is proposed by a pass transistor logic, instead of the inverter setup. A 4 bit serial in parallel out (SIPO) shift register is designed using the restructured DFF and the power and area is reduced by 59%, 12% respectively. The proposed system is implemented using Tanner 13.0 tool with 130 nm technology.