Multiple cell upsets (MCUs) are fetching major issues in the dependability of memories out in the open to radiation atmosphere. To stop MCUs from cause data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is higher delay overhead. In this paper, novel decimal matrix code (DMC) based on divide-symbol is projected to boost memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits. ERT uses DMC encoder itself to be part of the decoder. Occurrence of such errors in the configuration frames of a field-programmable gate array (FPGA) device permanently affects the functionality of the mapped design. In this paper, we present a low-cost error-detection code to detect MBUs in configuration frames as well as a generic scrubbing scheme to reconstruct the erroneous configuration frame based on the concept of erasure codes. The proposed scheme does not require any modification to the FPGA architecture. Implementation of the proposed scheme on a Xilinx Virtex-6 FPGA device shows that the proposed scheme can detect 100% of MCUs in the configuration frames with only 3.3% resource occupation, while the recovery time is comparable with the previous schemes.